TSMC Advanced Nodes and CoWoS Stay Sold Out as AWS and Google Reshape Capacity Allocation

TSMC's 3-nanometre, 2-nanometre and CoWoS advanced packaging capacity remained in short supply in the late third quarter of 2026, according to DIGITIMES, as changes in major customer orders and front-end and back-end supply models prompted the foundry to adjust its advanced capacity allocation. Nvidia and Apple continue to occupy the largest share of leading-edge wafer and packaging resources, while Amazon Web Services and MediaTek increase wafer starts. MediaTek is also competing for 2- and 3-nanometre capacity and CoWoS slots after winning Google TPU orders. Supply chain estimates put overall TSMC utilisation near 96.2%, with 16/12-nanometre through 2-nanometre nodes effectively at 100%.

Packaging, not wafer fabrication, is the binding constraint. The CoWoS supply-demand gap is running at roughly 20%, and while that is expected to narrow to about 10% by the end of 2026 and ease further in 2027, it remains the gating item for accelerator shipments. TSMC CoWoS monthly capacity is projected at around 120,000 to 140,000 wafers by the end of 2026 and roughly 200,000 wafers in 2027. CoWoS-L is the tightest sub-segment and is expected to account for about 75% of TSMC's CoWoS capacity in the fourth quarter, because larger AI chip package areas and higher HBM stack counts consume more packaging capacity per unit.

Overflow is reshaping the OSAT layer. Back-end CoWoS steps are being shifted to ASE and SPIL, Amkor and Powertech, with ASE and SPIL capacity expected to rise from about 30,000 wafers a month in 2026 to 50,000 in 2027 and Amkor from roughly 20,000 to 30,000. Powertech's packaging lines are already fully loaded, with order visibility extending to 2028. Substrate makers such as Samsung Electro-Mechanics are moving from traditional carrier boards toward co-developing packaging solutions, and display panel makers are leveraging large-format glass processing to enter fan-out panel-level and glass-based packaging.

Customer architecture choices are adding another layer of complexity. Google's next-generation TPU project, scheduled to enter mass production by the end of 2027, is set to adopt Intel's EMIB-T advanced packaging with MediaTek as ASIC partner, and Google is reportedly weighing a CoWoS fallback as EMIB-T substrate yields lag. Co-packaged optics, chiplets and glass substrates are increasingly common as packaging moves deeper into system-level design, according to an IMAPS Taiwan interview published by DIGITIMES. For accelerators, leading-edge logic wafers, CoWoS or EMIB-T packaging, substrates and materials must now arrive on the same production cadence, and any single shortfall delays shipments.

The tightness is no longer confined to leading-edge nodes. DIGITIMES warns that the scramble for mature-node chips required for AI-related peripheral applications may persist through 2028, making supply chain management a source of bargaining leverage. Strong demand is showing up in TSMC's financials, with August 2026 consolidated revenue jumping 53.3% to NT$514.81 billion. For buyers, the practical implication is that capacity allocation is now a multi-year negotiation covering wafers, packaging, substrates and mature-node components simultaneously rather than a single quarterly booking.