TSMC Advanced Nodes and CoWoS Stay Tight While 8-Inch Foundries Regain Pricing Power

TSMC's most advanced capacity is still the binding constraint in the logic supply chain. DIGITIMES reported that 3nm, 2nm and CoWoS advanced packaging remained in short supply late in the third quarter, with changes in major customer orders and front-end and back-end supply models forcing the foundry to reallocate advanced capacity. The customers involved span cloud ASIC programmes, merchant GPU buyers and mobile silicon, and the allocation shuffle matters more than headline capacity additions because lead times are set by packaging slots as much as by wafer starts. Reporting citing supply-chain sources puts TSMC's 8-inch fab utilisation above 100 percent, with sub-45nm processes fully loaded and order visibility extending to 2030.

That scarcity is translating into price. TSMC has told customers it will raise wafer prices by roughly 3 to 6 percent from January 2027, with the steepest increases on 2nm and 3nm, while mature and specialty nodes are negotiated case by case. The increases also help fund overseas expansion: building fabs in the United States is estimated to cost four to five times a comparable plant in Taiwan, and the initial 2nm ramp is expected to dilute gross margin by 3 to 4 percentage points, with overseas fabs adding a further 2 to 3 points over the next several years. Rivals including Samsung and Intel have struggled to match TSMC's yield and cadence at the leading edge, which limits customers' ability to push back on price.

Tightness is spilling into mature nodes as well. DIGITIMES reported that South Korea's DB HiTek is gaining pricing power as 8-inch foundry supply tightens, utilisation stays high and demand for power-management chips improves conditions across mature-node manufacturing. Demand from AI server infrastructure is pulling in supporting components — power-management ICs, microcontrollers, driver ICs, analogue devices and sensors — that are built on 8-inch lines, so capacity that was once considered surplus is now contested. Advanced packaging is also being re-architected around risk: Google's next-generation TPU programme is weighing a CoWoS backup option as EMIB-T substrate yields lag, an indication that buyers no longer assume a single packaging route will clear on schedule.