AMD Details EPYC 9006 Venice Lineup as Agentic AI Reshapes Server CPU Demand
AMD has laid out its biggest EPYC lineup yet on TSMC 2nm, with up to 256 Zen 6c cores, 16 memory channels and MRDIMM support at 12,800 MT/s for 1.6TB/s of bandwidth. Power envelopes climb to 600W as AMD splits the family between a large SP7 socket and a mainstream SP8 socket.
AMD has published the product stack for EPYC 9006 Venice, building both Zen 6 and Zen 6c compute chiplets on TSMC 2nm rather than splitting nodes as it did for Turin. Density gains let AMD load dense Venice parts with up to 256 cores, 64 more than 192-core Turin Dense chips, while the highest-core-count standard Zen 6 part disclosed so far falls to 96 cores from 128. Fastest Zen 6 chips top out at 5.0GHz, matching Turin, while dense Zen 6c chips reach 4.1GHz, about 400MHz higher than Turin Dense. Every CCD is paired with 4MB of L3 cache per core, so high-performance parts reach 384MB of L3 and dense parts up to 1024MB.
The new I/O die carries most of the platform uplift. Venice supports 16 memory channels, up from 12 on Turin, and pushes DDR5 RDIMMs to 8,000 MT/sec with MRDIMM support reaching 12,800 MT/sec, giving up to 1TB/s with RDIMMs and 1.6TB/s with MRDIMMs. The die also adds PCIe 6 and CXL 3.1, doubling I/O bandwidth, with up to 128 lanes of PCIe or CXL in a single-processor configuration. Intel and AMD now share cache-coherent CPU-to-GPU connectivity: Venice speaks the same xGMI flavour as the Instinct MI455X, letting GPUs hold a coherent window into the CPU memory pool instead of linking only over PCIe.
Power is the constraint vendors now design around. The 192- and 256-core Venice parts top out at a 600W TDP, a full 100W above Turin's ceiling, while high-frequency Zen 6 parts reach 500W, higher on a watts-per-core basis than Turin. Within the SP7 flagship socket, buyers can choose up to 256 cores and 512 threads in a 600W part or 96 cores at up to 5GHz in a 500W part; five of the nine public SKUs are 500W and two more are 600W. The SP8 socket scales from 130W to 400W and from 8 to 128 cores, mirroring Intel's split between Xeon 6900P and 6700P series parts. AMD is keeping the I/O die on TSMC 6nm, which also frees leading-edge wafer allocations for the compute chiplets.
Rack-scale demand is pulling the roadmap in two directions at once. An EPYC 9006X variant with roughly 1.1GB of L3 cache targets HPC buyers who want bandwidth and per-core performance rather than maximum vCPU density, while an EPYC 9006 LP part brings LPDDR5X to EPYC for the first time and competes directly with NVIDIA Grace and Vera CPUs destined for Helios racks. On the ODM side, Chenming Electronic Tech president Charles Lo said L11 system integration reached 18% of revenue in January to August 2026, with new models such as VR200 entering mass production in the fourth quarter.