Advanced Packaging Becomes Chip Equipment's Next Battleground as ASML Eyes a Hybrid Bonder

As it becomes harder and costlier to shrink transistors, advanced packaging has become the place chip equipment makers look for their next leg of growth, and ASML appears to be preparing its second move into it. Patent filings analysed by research firm SemiAnalysis suggest the Dutch lithography leader is building a die-to-wafer hybrid bonder, a tool that would pit it against Besi, the current leader in the segment, and a growing group of front-end rivals chasing the same market. The move matters because hybrid bonding is the interconnect step that underpins HBM stacks and chiplet-based AI accelerators, so control of that toolset is becoming strategically as important as lithography itself.

TrendForce's latest research on AI interconnect technologies shows the same shift happening in test. Demand for high-speed transmission in AI datacentres is pushing co-packaged optics toward mass production, making shorter test times and lower costs increasingly important, and raising demand for integrated test equipment and software because CPO requires coordinated electrical and optical measurement. Optical alignment times have already fallen to second or even sub-second levels, but a complete test of a single photonic integrated circuit can still take over 100 seconds, so the mass-production bottleneck has moved from alignment accuracy to test speed. Testing a CPO device currently requires laser sources, optical switches, optical power meters and optical spectrum analysers, and equipping every station with a full set leaves expensive instruments underutilised.

The competitive response is already visible. TrendForce identifies seven segments in the CPO testing supply chain and says value is shifting from individual instrument performance to the ability to integrate complete production-test platforms. Teradyne acquired Quantifi Photonics in 2025 to strengthen optical measurement; Advantest announced a collaboration with VIAVI and SENKO in September 2026 covering automated testing, optical measurement and detachable optical interfaces, and the partners demonstrated a simulated CPO production test workflow at ECOC 2026. Taiwan's GMT Global supplies multi-axis coupling and alignment modules, MPI offers probing and alignment equipment, WinWay covers test interfaces and Chroma automated and burn-in test, while ASE bridges packaging and production test; China's Semight has begun volume shipments of a 65 GHz sampling oscilloscope but still relies heavily on imported high-end instruments.

TrendForce expects 2027 to be a pivotal year for the convergence of CPO test architectures and equipment investment strategies, with 2028 the critical period for validating readiness for large-scale mass production. Packaging substrates are moving on the same clock: DIGITIMES reported that LG Innotek expects to begin supplying glass substrates for advanced semiconductor packaging around 2028 as it expands beyond smartphone camera modules. Together these point to a capex cycle in which the constraint on AI silicon is shifting away from the front-end lithography bottleneck and toward the back-end steps - bonding, substrates and test - that determine how many good packages actually ship.