TSMC Runs Near Full Utilisation as CoWoS Tightness Spills Over to OSATs

TSMC's 3nm, 2nm and CoWoS advanced packaging capacity remained in short supply in late third-quarter 2026 as changes in major customer orders prompted the foundry to adjust its advanced capacity allocation, supply chain sources said. Monthly 3nm output reached about 185,000 wafers in late September, while combined 2nm capacity stood at roughly 50,000 wafers each at Hsinchu Fab 20 and Kaohsiung Fab 22. Overall utilisation was estimated at about 96.2%, with nodes from 16/12nm to 2nm running at 100%, 45nm at 97% and 8-inch fabs also close to full. TSMC is continuing to convert some 5nm equipment to 3nm, with a new 3nm line in the Southern Taiwan Science Park expected to enter mass production in the first half of 2027.

Customer mix is shifting underneath the constraint. Nvidia and Apple continue to dominate TSMC's advanced process and packaging resources, but AWS has expanded Annapurna AI chip tape-outs, raising its priority in 3nm and CoWoS allocation, with partners including Alchip, Marvell and more recently Qualcomm. MediaTek won Google TPU orders, and the next-generation TPU v9 is set to use both TSMC CoWoS-L and Intel EMIB-T, changing the front-end and back-end supply model and prompting a slight adjustment to MediaTek's 3nm and 2nm planning. MediaTek's 3nm TPU v8t is expected to begin mass production in the fourth quarter and ramp through 2027, and the company has brought in retired TSMC veterans to help resolve mass-production and supply-chain coordination issues.

The packaging bottleneck is redistributing rather than easing. Spillover orders go first to ASE's SPIL, then Amkor and Powertech; although Powertech ranks lower in the queue, its packaging capacity is already fully utilised and order visibility extends to 2028. TSMC is also deepening its domestic supply chain: construction of Kaohsiung's Baipu Industrial Park began on September 21 with TSMC expected to anchor the cluster, and the company plans a mini-loop line there to speed CoWoS equipment and materials validation. Separate reports say TSMC is also considering an AUO site for CoPoS panel-level packaging, which would extend competition beyond the traditional OSAT base.

Policy risk is layering on top of the capacity constraint. On September 14 the European Commission adopted an update to the EU dual-use export control list adding semiconductor manufacturing and testing equipment, including atomic layer deposition tools, EUV mask development and inspection equipment and single-wafer cleaning tools, along with certain advanced computing integrated circuits and silicon carbide fibre production equipment. The measures take effect only after publication in the EU Official Journal and a two-month scrutiny period. For equipment makers, foundries and OSATs, longer certification, upgrade and installation cycles are becoming a planning assumption rather than a tail risk.