TSMC Runs 96.2% Utilization as CoWoS Shortage Redirects Packaging Orders to OSATs

TSMC's advanced nodes remain the binding constraint on AI silicon supply. Supply-chain sources put overall utilisation at about 96.2% at the end of September, with 16/12nm through 2nm running at 100%, 45nm at 97%, and 8-inch fabs also close to full. Nvidia and Apple continue to dominate advanced process and packaging resources, while Amazon's AWS unit Annapurna has expanded AI chip tape-outs and secured more 3nm capacity. MediaTek, beyond its phone business, is competing for 2nm and 3nm plus CoWoS-S/L capacity after winning Google TPU orders, and has brought in retired TSMC veterans to coordinate the foundry, packaging, substrate and materials supply chains that TPU mass production requires.

Capacity is being reallocated rather than expanded fast enough. TSMC's 2nm output is set to reach about 50,000 wafers a month each at Hsinchu's Fab 20 and Kaohsiung's Fab 22 by the end of October, roughly 100,000 wafers combined, while southern Taiwan's 3nm capacity is on track for about 185,000 wafers a month over the same horizon. The foundry is converting some 5nm equipment to 3nm, with a new 3nm line in the Southern Taiwan Science Park due to enter mass production in the first half of 2027; its second Arizona fab and second Japan fab are also planned for 3nm. MediaTek's 3nm TPU v8t is expected to begin mass production in the fourth quarter and ramp through 2027, and the next-generation TPU v9 will use both TSMC CoWoS-L and Intel EMIB-T, changing the front-end and back-end supply model.

Packaging is the tightest link. CoWoS supply is estimated to be running about 20% short of demand, a gap that TSMC and its partners are expected to narrow to roughly 10% by the end of 2026 and ease further in 2027 as capacity is added. Spillover orders are going first to SPIL within the ASE group, then to Amkor and Powertech; Powertech's packaging capacity is already fully utilised, with order visibility extending to 2028. Wider market reporting puts CoWoS lead times beyond 52 weeks, and the constraint is compounded by heavier HBM content per package, which raises the packaging area consumed for every accelerator shipped.

Mature nodes are tightening for different reasons. A 15 September analysis of the 24-55nm band pointed to lengthening lead times, with the Commodity IQ Lead Time Index rising from 157.5 in the first quarter of 2026 to 179.6 in the second and 191.4 in the third, as AI pulls fab investment toward leading-edge capacity while China's domestic mobile-chip push competes for the same mature tools. Higher copper prices are also lifting packaging quotes in parts of the chain, adding bill-of-materials pressure even where wafers are not the binding constraint. The same digest, citing Reuters, noted that a Taiwanese union representing Micron workers kept strike preparations alive over a permanent profit-sharing demand, a labour risk layered on top of an already sold-out DRAM and HBM base.