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Nvidia Bankrolls a Multi-Billion-Dollar CoWoS Expansion at SPIL as Packaging Becomes the AI Bottleneck

Nvidia is providing billions of dollars in financing to expand CoWoS advanced-packaging capacity at Siliconware Precision Industries, Reuters reported, as Yole Group forecasts advanced packaging revenue will overtake traditional packaging for the first time in 2026 with capital spending near $28 billion.

Nvidia is bankrolling a multibillion-dollar expansion of CoWoS advanced-packaging capacity at Siliconware Precision Industries, a unit of Taiwan's ASE Technology, an industry executive told Reuters in a November 6 feature on the packaging race. The funding, whose scale has not previously been reported, will pay for new factory space and equipment as TSMC's capacity limits push the world's largest AI accelerator designer to secure back-end supply outside the foundry it relies on for front-end manufacturing. Nvidia declined to comment and ASE said it does not comment on market rumors involving its customers.

The money is part of a broader repricing of what was once the least glamorous step in chipmaking. Research firm Yole Group forecasts that revenue from advanced packaging will overtake traditional packaging for the first time in 2026, with capital spending on the technology expected to near $28 billion, and former Intel chief executive Pat Gelsinger estimated that advanced packaging could eventually account for as much as half the value of a chip product. AMD has unveiled more than $10 billion of investments across Taiwan's semiconductor industry, including packaging partnerships with ASE, SPIL and Powertech.

The scramble is spreading to panel-level formats that promise larger packages and less wasted material. Powertech Technology plans a $400 million advanced-packaging joint venture with Broadcom in Singapore with production that could begin in 2028, its chairman D K Tsai said, adding that everyone is looking for a solution outside TSMC. TSMC itself is developing a panel-based successor called CoPoS, with a pilot line built as of April and production expected within a couple of years, though CoWoS remains its main AI packaging technology.

For the AI hardware market the signal is that packaging capacity, not wafer starts, is now the binding constraint on accelerator output. Chip designers are responding by funding the constraint directly, an approach that eases supply but ties their product roadmaps to a handful of back-end partners, and it explains why packaging lead times and prices have become as closely watched as HBM allocation through the 2027 buildout.

Sources