TSMC 3nm, 2nm and CoWoS Stay Sold Out as AWS and Google TPU Orders Reshape Allocation
TSMC's 3nm, 2nm and CoWoS capacity remained in short supply in late Q3 2026, forcing a reallocation as AWS lifts Annapurna tape-outs and MediaTek pulls TPU volume. Overall utilisation is running near 96%, with advanced nodes at 100% and packaging overflow reaching OSATs through 2028.
TSMC's 3nm and 2nm logic capacity and CoWoS advanced packaging remained oversubscribed into the second half of September 2026, and changes in major customer orders have pushed the foundry to reallocate advanced capacity. Nvidia and Apple continue to hold the largest share of leading-edge resources, but Amazon's AWS has increased AI chip tape-outs through its Annapurna unit and secured more 3nm capacity, while MediaTek is competing for 2nm and 3nm slots and CoWoS-S and CoWoS-L capacity on the back of Google TPU orders.
The back-end configuration is shifting with it. After winning the Google TPU programme, MediaTek's next-generation TPU v9 is set to use both TSMC CoWoS-L and Intel EMIB-T, a change in front-end and back-end supply model that has already led to adjustments in its 3nm and 2nm allocations. Google's Humufish TPU project, scheduled for mass production by the end of 2027, is adopting Intel EMIB-T with MediaTek as ASIC partner, though EMIB-T substrate yields are lagging enough that Google is weighing CoWoS as a backup for 2027.
TSMC has been expanding rapidly but from a fully loaded base. Two-nanometre monthly capacity at Hsinchu's Fab 20 in Baoshan and Kaohsiung's Fab 22 is set to reach roughly 50,000 wafers each, about 100,000 combined, by the end of October, while southern Taiwan 3nm capacity rises to about 185,000 wafers per month. Overall utilisation is estimated near 96.2% at the end of September, with 16nm and 12nm through 2nm running at 100%, 45nm around 97% and 8-inch fabs close to full.
Packaging, not wafer starts, is the binding constraint. CoWoS shortages are spilling advanced packaging orders to outsourced assembly and test houses, with ASE's SPIL first in line followed by Amkor and Powertech; Powertech's relevant capacity is already fully loaded with order visibility extending to 2028. TSMC is also converting some 5nm equipment to 3nm, with a new southern Taiwan 3nm line due to enter mass production in the first half of 2027 and 3nm planned for its second Arizona fab and second Japan fab.