TSMC Flags Equipment, Labour and Infrastructure Strain as AI Demand Outpaces Planning

TSMC says surging artificial intelligence demand is stretching the global chip industry beyond its usual planning cycle, with fast-changing procurement needs, labour shortages and infrastructure constraints affecting markets well beyond Taiwan. The foundry has responded by stepping up equipment purchasing, a shift that is being felt across the Taiwanese supply chain from gas and materials handling to industrial PCs. Its 5nm, 4nm and 3nm nodes are running at full capacity on AI server chip demand, and the company holds about 72.5% of the global foundry market.

Demand shows up clearly in the numbers. TSMC reported August revenue of NT$514.8 billion, roughly $16.35 billion, up 53.3% year on year and 10.1% sequentially, a fourth consecutive month of growth, and has guided third-quarter revenue to $44.6-45.8 billion. Equipment makers are scaling with it: Taiwanese gas equipment supplier JM-Applied, which counts Micron and TSMC in its customer base, said first-half 2026 revenue passed NT$600 million, up more than 50% year on year, with an order book above NT$3 billion.

On lithography, ASML issued joint statements with Intel Foundry, TSMC and Samsung Electronics on 8 September, converging the three leading-edge chipmakers on a transition from the industry's decades-old 6-inch photomask to a larger 12-inch format for High-NA EUV. The move is aimed squarely at data-centre dies: current High-NA tools use a smaller mask that limits maximum chip size, and ASML has estimated a roughly 40% improvement in system productivity from the switch. TSMC has talked about adopting High-NA for advanced-node production around 2030, while Samsung has targeted 2028 for DRAM.

Advanced packaging remains the binding constraint. TSMC's CoWoS capacity for 2027 is reported fully booked, with some customers turning to Intel's EMIB-T as an alternative, and the chiplet packaging market is growing at roughly a 42.5% compound annual rate. TSMC is also asking HBM and DRAM makers to make future designs more compatible with X-ray inspection, as increasingly complex packages make buried defects harder to detect while raising concerns about radiation exposure to sensitive memory devices. In a related attempt to relieve the memory bottleneck, SK Hynix and SanDisk published the first open standard for High Bandwidth Flash, a tier between HBM and SSDs offering up to 512GB at 0.4-3.0 TB/s over UCIe, with Google and Tenstorrent joining the consortium.